How to use the undefined delay ($) in SVA

SystemVerilog
1

How ##[1:] behave in sva. how to control the assertion in sva If we don't know the exact delay. because while failing the condition ##[1:] delay is not working.

2

In reply to mukeshkumar.saha@reliabletechsys.com:

You need to clarify your question, possibly with an example.
In any case,

  1. the sequence (a ##[1:$] b) is same as
    (a ##1 b) or (a ##2 b) or …(a ##n b) // where n is infinity
  2. is a sequence in an antecedent has multiple possible matches, then all possible matches need to be tested. Thus,
    (a ##[1:] b) |-> c // can fail, but will never succeed because of above explanation. The fix first_match((a ##[1:] b) |-> c
  3. if consequent, the first_match is not needed because assertion will pass on a success.
    c |-> (a ##[1:$] b) // OK

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

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