How to use the arguments of two different sequences for comparing in a third sequence using Assertions?

SystemVerilog
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7

In reply to ben@SystemVerilog.us:

I thought of using a task which will produce delay of one posedge of scl.

BTW, firing a task from a sequence_match_item just fires it, like a function call. There is no time consumption in the assertion.
It is discouraged to use tasks; I haven’t chhecked, but I believe it might be illegal. If legal, it does nothing for the assertion (no time consumption processed by the assertion as a result of the task call). You can use functions that consume no time.
Ben SystemVerilog.us