How to use ' strong ' with ' throughout ' Operator

SystemVerilog
,
1

I am trying to use ’ strong ’ operator along with ’ throughout ’ expression in below code ::


property  through_out ;

  tErrorBit  throughout  ( $rose( mCheck ) [ -> 1 ] )  ;

endproperty

property  ab ;

   @( posedge  clk )   $rose( tErrorBit )  |->  strong( through_out ) ;  //  This  is  Illegal 
   
endproperty

Any suggestions ?

2

In reply to hisingh:

Declare
through_out as a sequence, not a property.

3 

strong  N   weak  operator  can  ONLY  be written  for  sequence_expression

Thanks , Dave