In a Block if we are extracting a path from a file which is pointing to a variable in string format and that is changing as per dependency. so as in uvm_hdl_read we use to give string as 1st argument and that string is represent a variable which we could store in other variable. can we do that in system verilog.
As example i’m showing a simple code:
class tb;
int t =1;
endclass
module tb;
tb t_h = new();
int x;
initial begin
string a = "t_h.t";
x = a; // requirement is simulator should see it as x = t_h.t instead of x = "t_h.t";
// x should store the int value of t variable from class tb.
$display("value of %s",t_h.t);
$display("value of %d",x);
end
endmodule
is it possible to get same value in both display?