How to use parameter as the condition of conditional compile(`ifdef)

SystemVerilog
1 
module delay_ff
#(
	parameter C_d = 2
)
(
	input logic clk,
	input logic rst,
	input logic din,
	`ifdef C_d==2    // how??
	output logic dout_d1, dout_d2,
	`elif C_d==1
	output logic dout_d1,
	`endif
	
	

);

logic dout_d1, dout_d2, dout_d3;
generate 
	if(C_d==1) begin
		always_ff @(posedge clk) begin
			dout_d1 <= din;
		end
	end 
	else if(C_d==2) begin
		always_ff @(posedge clk) begin
			dout_d1 <= din;
			dout_d2 <= dout_d1;
		end
	end
	else if(C_d==3) begin
		always_ff @(posedge clk) begin
			dout_d1 <= din;
			dout_d2 <= dout_d1;
			dout_d3 <= dout_d2;
		end
	end
endgenerate

endmodule
2

Macros are pre-processor compiler directives. That means macros get processed before any SystemVerilog syntax gets parsed - before the compiler knows about parameter definitions.

You could try to use an unpacked array rather than individual signals.

module delay_ff
#(
	parameter C_d = 2
)
(
	input logic clk,
	input logic rst,
	input logic din,
	output logic dout[C_d]
};