How to use modport in driver and monitor independently?

SystemVerilog
1

In my testbench I have created a interface file

interface intf
  logic clk;
  logic busy;
  logic data;
  modport in(input clk,busy,data);
  modport out(input clk,output busy,data);
endinterface

In my top module I have instantiated and set the interface in this way

intf if();
initial begin
   uvm_config_db#(virtual intf.in)::set(uvm_root::get(), "*", vif_mon,if.in);
   uvm_config_db#(virtual intf.out)::set(uvm_root::get(), "*", vif_drv,if.out);
end

And In my driver class I have declared virtual Interface as

virtual intf.out vif;
uvm_config_db#(virtual intf.out)::get(this, *,vif_drv,vif)

And In my monitor class I have declared virtual Interface as

virtual intf.in vif;
uvm_config_db#(virtual intf.in)::get(this, *,vif_mon,vif)

Driver is using OUT modport to drive signals to RTL where as monitor is using IN modport to capture signals from RTL.

What I can see in my testbench is the time driver is asserting ho_busy(Using out modport) at the same time IN modport ho_busy is getting asserted. Because of which my monitor start capturing data.

Is there a way I can pass modport independently to driver and monitor?

cc: @dave_59

2

Hi, modports are just direction specifiers and so all modports still share same interface signals. what is your requirement here? as per your code as there is no ‘valid’ signal, assuming data signal will be sent when ‘busy’ asserted. So, when bust asserted, there will be valid data in DUT interface and same will be captured by monitor. you can try using clocking blocks to control the sample and hold timings.

3

Modports are design constructs and shouldn’t be used for verification. You should use clocking blocks if you feel it necessary to group signals with direction.

I’m not sure what the issue is with your current code. When the driver asserts ho_busy, the monitor sees the same signal. This would be expected behavior. What do you expect to occur?