enum int { ACT=0, WRITE=1, READ=2, PRE=3, REF=4} val;
class sdram_sequence_item extends uvm_sequence_item;
val cmd;
reg [7:0] data_in;
reg [7:0] col_addr;
reg [1:0] row_addr;
reg [1:0] bank_sel;
reg act_cmd;
reg pre_cmd;
reg ref_cmd;
reg read_cmd;
reg write_cmd;
wire dqs_in; // To DUT active high
wire dqs_out; // From DUT
reg data_mask;
reg [7:0] data_out;
reg write_active;
wire dqs_inout;
// int delay_pre;
// int delay_p1;
`uvm_object_utils(sdram_sequence_item)
function new(string name = "");
super.new(name);
endfunction
endclass
/////Act/////
class sdram_activate_cmd extends sdram_sequence_item;
val cmd;
rand bit [1:0] row_addr;
rand bit [1:0] bank_sel;
int delay_pre;
int delay_p1;
`uvm_object_utils(sdram_activat_cmd)
function new(string name = "");
cmd=ACT;
delay_pre=0;
delay_p1=4;
super.new(name);
endfunction
endclass
////write////
class sdram_write_cmd extends sdram_sequence_item;
val cmd;
int delay_pre;
int delay_p1;
`uvm_object_utils(sdram_write_cmd)
rand [1:0] bank_sel;
rand bit [7:0] col_addr;
rand bit [31:0] data_in;
function new();
super.new(name);
cmd=WRITE;
delay_pre=0;
delay_p1=4;
endfunction
endclass
//////READ//////
class sdram_read_cmd extends sdram_sequence_item;
val cmd;
int delay_pre;
int delay_p1;
`uvm_object_utils(sdram_read_cmd)
rand [1:0] bank_sel;
rand bit [7:0] col_addr;
bit [31:0] data_out;
function new();
super.new(name);
cmd=READ;
delay_pre=0;
delay_p1=4;
endfunction
endclass
/////Pre//////
class sdram_pre_cmd extends sdram_sequence_item;
val cmd;
int delay_pre;
int delay_p1;
`uvm_object_utils(sdram_pre_cmd)
function new();
super.new(name);
cmd=PRE;
delay_pre=0;
delay_p1=10;
endfunction
endclass
/////REF/////
class sdram_ref_cmd extends sdram_sequence_item;
val cmd;
int delay_pre;
int delay_p1;
`uvm_object_utils(sdram_ref_cmd)
function new();
super.new(name);
cmd=REF;
delay_pre=0;
delay_p1=64;
endfunction
endclass
class act_seq extends uvm_sequence#(sdram_activate_cmd);
`uvm_object_utils(act_seq)
function new(string name="");
super.new(name);
endfunction
virtual task body();
sdram_act_cmd act;
act= sdram_activate_cmd::type_id::create("req");
start_item(act);
if(!act.randomize())begin
`uvm_error("act_cmd","Randomize Failed")
end
finish_item(act);
endtask
endclass :act_seq
class wr_seq extends uvm_sequence#(sdram_write_cmd);
`uvm_object_utils(wr_seq)
sdram_write_cmd write;
function new(string name="");
super.new(name);
endfunction
virtual task body();
write = sdram_write_cmd::type_id::create("write");
start_item(write);
if(!write.randomize())begin
`uvm_error("write_cmd","Randomize Failed")
end
finish_item(write);
endtask
endclass:wr_seq
class rd_seq extends uvm_sequence#(sdram_read_item);
`uvm_object_utils(rd_seq)
sdram_read_cmd read;
function new(string name="");
super.new(name);
endfunction
virtual task body();
read= sdram_read_cmd::type_id::create("read");
start_item(read);
if(!read.randomize())begin
`uvm_error("read_cmd","Randomize Failed")
end
finish_item(read);
endtask
endclass :rd_seq
class ref_seq extends uvm_sequence#(sdram_ref_cmd);
`uvm_object_utils(ref_seq)
sdram_ref_cmd refr;
function new(string name="");
super.new(name);
endfunction
virtual task body();
refr= sdram_ref_cmd::type_id::create("ref");
start_item(refr);
if(!refr.randomize())begin
`uvm_error("ref_cmd","Randomize Failed")
end
finish_item(refr);
endtask
endclass :ref_seq
class pre_seq extends uvm_sequence#(sdram_pre_cmd);
`uvm_object_utils(_seq)
sdram_pre_cmd pre;
function new(string name="");
super.new(name);
endfunction
virtual task body();
pre= sdram_pre_cmd::type_id::create("pre");
start_item(pre);
if(!pre.randomize())begin
`uvm_error("pre_cmd","Randomize Failed")
end
finish_item(pre);
endtask
endclass :pre_seq
// class ul_sequence extends uvm_sequence#(sdram_sequence_item);
// `uvm_object_utils(ul_sequence)
// function new(string name = "ul_sequence");
// super.new(name);
// endfunction
// virtual task body();
// endtask
class sdram_act_wr_rd_pre_seq extends uvm_sequence#(sdram_sequence_item);
`uvm_object_utils(sdram_act_wr_rd_pre_seq)
function new(string name = "");
super.new(name);
endfunction
virtual task body();
act_seq act_sequence;
wr_seq write_sequence;
rd_seq read_sequence;
pre_seq precharge;
ref_seq refresh;
// ACT
act_sequence= act_seq::type_id::create("act_sequence");
start_item(act_sequence);
if (!act_sequence.randomize()) begin
`uvm_error("act_cmd", "Randomize Failed")
end
finish_item(act_sequence);
//WRT
write_sequence = wr_seq::type_id::create("write_sequence");
start_item(write_sequence);
if (!write_sequence.randomize()) begin
`uvm_error("write_seq", "Randomize Failed")
end
finish_item(write_sequence);
//Rd
read_sequence=rd_seq::type_id::create("read_sequence");
start_item(read_sequence);
if (!read_sequence.randomize()) begin
`uvm_error("read_seq", "Randomize Failed")
end
read_sequence.finish_item(read_sequence);
//Pre
precharge = pre_seq::type_id::create("precharge");
start_item(pre);
if (!precharge.randomize()) begin
`uvm_error("pre_seq", "Randomize Failed")
end
finish_item(precharge);
// REF
refresh = ref_seq::type_id::create("refr");
start_item(refresh);
if (!refresh.randomize()) begin
`uvm_error("refr_cmd", "Randomize Failed")
end
finish_item(refresh);
endtask
endclass
class lo_seq extends uvm_sequence#(sdram_sequence_item);
`uvm_object_utils(lo_seq)
function new(string name = "");
super.new(name);
endfunction
virtual task body();
sdram_sequence_item ll;
sdram_act_wr_rd_pre_seq ul;
repeat(8) begin
`uvm_info(get_type_name(),"------------Sending DATA to Driver----------------------",UVM_NONE)
req = sdram_sequence_item ::type_id::create("req");
start_item(req);
if (!req.randomize()) begin
`uvm_error("MY_SEQUENCE", "Randomize failed.");
end
finish_item(req);
end
endtask: body
class sdram_sequencer extends uvm_sequencer#(sdram_sequence_item);
`uvm_component_utils(sdram_sequencer)
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction
endclass :sdram_sequencer
Now how to give my act_pre_wr_wr_rd_rd_rd_ref and another sequence as act_wr_rd_pre_ref to low level sequence and then to driver?