How to use input variables when forking the same task multiple times

SystemVerilog
, ,
1 

event E_TRIGGER1;

  module top();
      
    initial begin
       fork
          printme(0,3);
          printme(1,4);
          control();
        join    
    end
   endmodule

  task control();
        #10;
        ->E_TRIGGER1;
  endtask
    
  task printme(input int i1, input int i2);
    if (i1==0) begin
        @E_TRIGGER1;
        $display("entered (i1==0), value i1=%d, i2=%d", i1, i2);
    end
    else begin
        $display("entered (else), value i1=%d, i2=%d", i1, i2);
    end
  endtask

I want to fork the same task multiple times but change their behavior using different input variables.
However, when I run the example above, the simulator produces the following output:

entered (else), value i1=          1, i2=          4
entered (i1==0), value i1=          1, i2=          4

I don’t understand how the second line can be generated with i1=1 and i2=2. It seems to me as if these variables are overwritten while waiting for the event by the second fork of the task. Doesn’t have a forked task it’s own copy of the input variables on it’s stack? If I remove the @E_TRIGGER1; the output is as I expect it also to be in the example:

entered (i1==0), value i1=          0, i2=          3
entered (else), value i1=          1, i2=          4
2

In reply to moses_rotesmeer:
Declare the task with an automatic lifetime.

See what is the exact difference between static tasks/functions and automatic tasks/functions ? please explain with a clear example | Verification Academy