How to use genvar or generate block in uvm sequence

UVM
1

Hi,
I want to probe some signals inside DUT.

I have 64 “stream_gates” inside the DUT. I wanted to implement a genvar variable to access a particular signal inside each of the gates…But it gives me below ERROR:

My code >>>>>>>>>>>>>>>>
genvar ki;
for ( ki=0; ki<63; ki++) begin
if(sw_tb_top.u_dut_top.u_swsys.stream_gates[ki].u_psfp_sg.gate_enabled != 1’b1)`uvm_error(“RDB_CHECK_FAIL”,$psprintf(“gate_enable[%0d] is not equal to 1’b1. Expected is 1’b1”,ki));
end

Error >>>>>>>>>>>>

Verilog keyword ‘genvar’ is not expected to be used in this context.

Can you please help me figure out how I can do this? Can’t I use genvar inside a class??

Thanks

2

In reply to kartavya:

genvar is usually used in testbench, which is a module
i don’t think you can use generate syntax in a class(like uvm_sequence)

besides, i don’t think you need generate in such scenario but just a simple for loop is OK

generate syntax treat block execute parallelly while your code cosume no simulation time