How to use enum type in for loop in systemverilog?

SystemVerilog
,
1

Dear All,

I’m trying to implement the enum type in for loop in systemverilog.

enum index { 0xa3, 0x07, 0x18};

for(i=0xa3 ; i<0x18; i++) {
printf(“data is %x”, i);
}

As I know enum is not array. iy’s constant. so it need a stack variable.
this is quite different way from C.

How to use enum type in for loop by systemverilog?
Can I use enum type directly into for loop?

2

In reply to UVM_LOVE:

Perhaps you are looking for enum_var.first, next() and last() methods.

Cheers
Srini

3

This example loops through the enum

typedef enum {GREEN=2, YELLOW=3, RED=4, BLUE=5} colors;

module tb;
  initial begin
    colors color;
      
    // Assign current value of color to GREEN
    color = GREEN;
      
    do begin
      $display ("color.name()  = %s, color = %0d" , color.name(), color);
      color = color.next();
    end while(color != color.first());
  end
endmodule