Hi All,
$rose(b) |-> a[*3];
Whenever the b goes 0 to 1. The next 3 continues clock cycles a should be true.
$rose(b) |-> a[*value];
If i am give value instead of 3.
i am getting error like "Illegal operand for constant expression".
Because my case 3 is not fixed.It's changing at any time.
So any idea to how to check this scenario.
Thanks in Advance
Rajaraman
In reply to Rajaraman Rak7:
You can use count variable in property assrtion:
property p;
int count;
@(posedge clk) disable iff(!resetn);
($rose(b), count = 0) |-> first_match((a, count = count + 1)[*1:$] && (count == 3));
endproperty
You can change any count value you want.
In reply to chrisle:
See my paper http://systemverilog.us/vf/SolvingComplexUsersAssertions.pdf
SOLUTION: Reference ii (at end of this paper) provides a solution for handling dynamic delays an repeats using tasks. However, in the Forums: SystemVerilog | Verification Academy forum, a user brought up a very interesting alternative that uses a package; it is presented here. The concept is very simple, the repeat or delay sequence is saved in a package with two defined sequence declarations that include arguments.
http://SystemVerilog.us/vf/sva_delay_repeat_pkg.sv
package sva_delay_repeat_pkg;
sequence dynamic_repeat(q_s, count);
int v=count;
(1, v=count) ##0 first_match((q_s, v=v-1'b1) [*1:$] ##0 v<=0);
endsequence
sequence dynamic_delay(count);
int v;
(1, v=count) ##0 first_match((1, v=v-1'b1) [*0:$] ##1 v<=0);
endsequence
endpackage
// The package can be applied as follows:
// http://SystemVerilog.us/vf/sva_delay_repeat.sv
import sva_delay_repeat_pkg::*;
module top;
timeunit 1ns; timeprecision 100ps;
bit clk, a, b, c=1;
int r=2;
default clocking @(posedge clk); endclocking
sequence q1; a ##1 b; endsequence
ap_abr: assert property(a |-> dynamic_repeat(q1, r) ##1 c);
ap_delay:assert property(a |-> dynamic_delay(r) ##0 b);
For your model:
$rose(b) |=> dynamic_repeat(a, value); // a[*value];
Whenever the b goes 0 to 1. The next 3 continues clock cycles a should be true.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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