How to use an input signal to control module parameter

SystemVerilog
1

like the following ex


module top(
input logic[1:0] a,
input logic clk
);

defparam inst.width = a;
cnt#(.width(a)) inst(.clk(clk));
endmodule
2

In reply to designer007:

Parameters are used during compilation/elaboration, while input signals change during run-time. You can’t change parameters during run-time.