How to trigger antecedent of this logic for SVA Assertion

SystemVerilog
,
1

I’m having hard time triggering antecedent of this assertion where sig_x is 8 bits. [7:0] sig_x;

property prop_name;
@(posedge clk) ((sig_x =='h0) && ($past(sig_x,1)=='h1) && ($past(sig_x,2)=='hc4) && ($past(sig_x,3) = 'h2c)) |-> .....((precedent logic));
endproperty

sig_x is always 0 but occasionally carries data packets and here I want it to trigger when it carries packet of 2c,c4,01 (each 8 bit per clock cycle @ time t,t+1,t+2 respectively) and I want it to trigger during the transition from t+2->t+3 when data goes from 'h01-> 'h00. But the log says antecedent cant be triggered but clearly I can see it exists in the waveform.

I also tried using sequences, Still same issue-

property prop_name;
@(posedge clk) ((sig_x=='h2c) ##1 (sig_x=='hc4) ##1 (sig_x=='h01)) |-> .....((precedent logic));
endproperty
2
  1. Why are you declaring a local variable?
  2. If sig_x is the design signal to be samples, then using it in the property.
  3. If you inended to use it as a formal argument, then it shoul be defined as such
    e.g. property name(logic [7:0] sig_x);

I believe that this is what you need.

property prop_name;
   @(posedge clk) (sig_x=='h2c) ##1
                                (sig_x=='hc4) ##1
                                (sig_x=='h01) ##1 1 |-> .....((consequent logic));
endproperty
// note:  
##1 1 |-> // is same as 
|=>
1 Like
3

My bad, sig_x is not a local variable its part of DUT, I wanted to convey its of 8 bits hence I wrote the line, let me rectify this.