When I ran a sequence from a task through the UVM test, the UVM objection mechanism propagation was broken. UVM simulation was terminated abnormally. Especially the driver does not finished correctly after my_test.my_run(32’h1234, 32’h12341234);
class my_test extends uvm_test;
...
rnd_seq_c rnd_seq;
function void build_phase(uvm_phase phase);
super.build_phase(phase);
rnd_seq = rnd_seq_c::type_id::create("rnd_seq", this);
endfunction
task run_phase(uvm_phase phase);
phase.raise_objection(this);
fork
my_test.my_run(32'h1234, 32'h12341234);
join
phase.drop_objection(this);
endclass
This is my sequence.
class rnd_seq_c extends vseq_c;
`uvm_objection_utils(rnd_seq_c)
function new(string name="rnd_seq_c ");
super.new(name);
endfucntion
virtual task my_run( bit [31:0] addr, bit [31:0] data);
rnd_item= rnd_seq_item::type_id::create("rnd_item");
start_item(rnd_item,,rnd_seqr);
rnd_item.data = data;
rnd_item.addr = addr;
finish_item(item);
endtask
endclass
pipelined driver used.
class my_pipelined_driver extends uvm_driver #(rnd_seq_c );
`uvm_component_utils(my_pipelined_driver)
/// Virtual Interface
virtual my_interface my_if;
/// Constructor
function new (string name, uvm_component parent);
super.new(name, parent);
endfunction: new
function void build_phase(uvm_phase phase);
super.build_phase(phase);
if(!uvm_config_db #(virtual my_interface)::get(this, "", "vif", my_if))begin
`uvm_fatal(get_type_name(), "Virtual Interface not set in my_driver")
end
else
`uvm_info(get_type_name(), "Virtual Interface set in my_driver", UVM_LOW)
endfunction
/// Semaphore Declaration
semaphore pipeline_lock = new(1);
/// Run Phase Task
task run_phase (uvm_phase phase);
@(posedge my_if.RESETn);
@(posedge my_if.HCLK);
fork
do_pipelined_transfer;
do_pipelined_transfer;
join
endtask: run_phase
/// do_pipelined_transfer task
task automatic do_pipelined_transfer;
// rnd_seq_c req;
forever begin
pipeline_lock.get();
seq_item_port.get_next_item(req);
accept_tr(req, $time);
void'(begin_tr(req, "pipelined_driver"));
my_if.HADDR <= req.HADDR;
my_if.HWRITE <= req.HWRITE;
my_if.HBURST <= req.HBURST;
@(posedge my_if.HCLK);
while(!my_if.HREADY == 1) begin
@(posedge my_if.HCLK);
end
// Command phase ends here
// Unlock semaphore
pipeline_lock.put();
// Data phase starts here
if (req.HWRITE == 0) begin
@(posedge my_if.HCLK);
while(my_if.HREADY != 1) begin
@(posedge my_if.HCLK);
end
req.HRDATA = my_if.HRDATA;
$display("!!Driver:read_data: %0h", req.HRDATA);
req.HRESP = my_if.HRESP;
end
else begin
my_if.HWDATA <= req.HWDATA;
@(posedge my_if.HCLK);
while(my_if.HREADY != 1) begin
@(posedge my_if.HCLK);
end
req.HRESP = my_if.HRESP;
end
// Return the Request as Response
seq_item_port.item_done(req);
end_tr(req);
end
endtask: do_pipelined_transfer
endclass: my_pipelined_driver
How do I run until the end of simulation from an abnormal termination?
fork
my_test.my_run(32’h1234, 32’h12341234);
join
If I use objection into the sequence,
class rnd_seq_c extends vseq_c;
`uvm_objection_utils(rnd_seq_c)
function new(string name="rnd_seq_c ");
super.new(name);
endfucntion
virtual task my_run( bit [31:0] addr, bit [31:0] data);
uvm_phase phase;
phase.raise_objection(this);
rnd_item= rnd_seq_item::type_id::create("rnd_item");
start_item(rnd_item,,rnd_seqr);
rnd_item.data = data;
rnd_item.addr = addr;
finish_item(item);
phase.drop_objection(this);
endtask
endclass
I get the NULL pointer dereference. Error. What if we start the sequence through task then how do I correctly start the sequence until end of test?