In reply to pinegreen:
The trick with the map(…) function I “borrowed” from the UVM user guide.
I didn’t know there was this crazy limitation to only add regs from the same block to a reg map. I guess you could work around it by declaring the system maps inside the system reg block and then pass the module reg blocks as parent arguments:
class system_reg_block extends uvm_reg_block;
module_reg_block module_block;
uvm_reg_map system_map;
virtual function void build();
system_map = uvm_reg_map::type_id::create("system_map", , module_block.get_full_name());
system_map.configure(module_block, ...);
endclass
endclass
It’s kind of like adding the system map inside the module level block, but this way you don’t touch the code for the module register block. You’ll have to see if there are any other repercussions of doing it like this.