How to support multiple register maps in a SOC system for a block with only one register map?

UVM
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2

In reply to pinegreen:

I remember trying this out too. The documentation was out of sync, stating that this should be possible, but the BCL gave the nice error message. You could go the long way of mapping all registers/memories into the top level maps and forget the map defined in the module register block:


class module_reg_block extends uvm_reg_block;
  // ...
  
  virtual function void build();
    default_map.add_mem(...);
    some_reg_file.map(default_map, ...);
  endfunction
endclass

Since we can’t add default map to multiple other maps, we’ll just have to remap:


class system_reg_block extends uvm_reg_block;
  module_reg_block module_block;

  // ...
  
  virtual function void build();
    master0_map.add_mem(module_block.mem, ...);
    module_block.some_reg_file.map(master0_map, ...);
    
    master1_map.add_mem(module_block.mem, ...);
    module_block.some_reg_file.map(master1_map, ...);
  endfunction
endclass

You could also refactor mapping register elements into a single function that takes the map as an argument to avoid duplication.