How do you stop a simulation in a controlled way?
Say my DUT receives bytes on it´s input and invert the data at the output.
To keep it simple: say I have sequencer, driver, my dut, and a monitor on the output.
My sequencer sends (by a mailbox) data a driver and together with a start_of_seq and a end_of_seq bit.
My sequencer knows from the test how many sequence_items to send, and then can stop
In my driver I have a while loop doing try_get on the incomming mailbox and looks for the end_of_seq bit, so can also be controlled to stop.
For example:
task run_phase()
while (end_of_seq == 1'b0)
begin
...
end
endtask
But my monitor doesn’t know how many data is comming and is running forever, in a while loop or in a for ever loop.
This constructions hangs up the simulation for ever.
task run_phase()
while (1) // Keep always running.
begin
...
end
endtask
How to close the monitor when you have send all test data?
How do you know when to close the monitor, keeping in mind that the DUT has x cycles of latency?
And how do you code this in SV?
It sounds like from this and your previous questions you are trying to duplicate what is already in the UVM and addressed by objections and timeouts. So my answer to your question is use the UVM.
I understand your reply. However “just use the UVM” is a too big risk for a small company, with a small group who does the RTL design and verification. I can not afford a UVM testbench which only is understood by one employee or a contractor. The risk is to high for a starting company.
I’m learning the concepts of verification by reading and looking at videos. I try to improve our testbenches gradually and apply them in SV language so that the whole team understands the code. So your obeservation is correct, I try to duplicate the UVM, but for a small part of it.
Yes it takes more time, yes it’s reinventing the wheel, yes there are people out there who does it in UVM. But if my testbench shows a failure I know who to fix it, or if we hit a problem in the field we know the code. If I have to use the UVM-testbench from a former collegue or contractor and can’t read the code, I have a much bigger problem.
I will strongly disagree with your statement and argue that not using UVM is a bigger risk than using it. UVM is an industry standard methodology. Your time would be better spent learning UVM implementation than trying to learn how to do the equivalent in SystemVerilog.
There are significant training resources available for UVM, and there are tools that can put together a complete UVM environment in a matter of hours with little UVM experience.
Investing the time now to start with UVM will pay significant dividends in the future.
You could adopt any one of these three topics independently, but they are much more powerful when put together. This all documented, and there is plenty of tutorial information on the web available that you won’t have to create.
But back to my question, how does a (UVM/OVM/SV/Verilog/VHDL) testbench stop simulating in a controlled manner?
How do you stop the ‘forever’ loops or while(1) loops?
Always setting the timeout to a long enough value is also not the way to go I suppose