Hi,
I am new to this forum, i learning system verilog by own . First i am understanding existing sv environment code for simple adder before developing by own. In environment we have so many blocks generator, driver ,receiver, score board, coverage, environment module, test case, test bench top. iam getting confusion that which block we need to develop first. Can anyone please explain me the flow of environment development. how to develop complete environment for simple design like adder.
Thanks in advance,
Please reply me as soon as possible.
In reply to nag_sv:
You seem to want to go toward UVM, but are looking for an approach that eases you nicely, and maybe slowly toward it. A question on this forum at the link below spurred me to add more info and details in my SVA Handbook 4th Edition.
See the following links:
TB architecture: TB architecture | Verification Academy
Cohen book: Testbench approacheshttp://systemverilog.us/svabk4_testing6.pdf
Those 2 links will help you get started and will help you transition easily into UVM if you need to. A word of advice:
DON’T IGNORE THE VALUE OF ASSERTIONS!!!
I address that in the first link above in one of my answers.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115