How to start a testbench at rising edge of a signal

SystemVerilog
1

Have two signals.
Need to start testbench at the rising edge of signal1,
and stop the testbench at the falling edge of signal2.

How to achieve that? Thank you.

2

In reply to newbeeAllen:

The answer really depends on which testbench methodology you are using, and where the signals are in relationship to any interfaces and clocks you have defined.

3

In reply to dave_59:

Simplified/stupid answer could be:

Need to start testbench at the rising edge of signal1,

@(posedge signal1)
start_your_tb; // Assuming it is a task

and stop the testbench at the falling edge of signal2.

Easier…
always @(negedge signa2)
$stop/$finish(2);

:-)

Srini