I am writing a testbench and have to set up an appropriate drain time for it. The time required by the dut to process the input sequences greatly depends on how many sequences I drive in, and the time to process the remaining transactions in the dut after the last sequence is sent in varies. How can I make the simulation stop at a specific condition like
if( output_pkt_no == some_value)
stop_simulation
And in which component of the testbench should I make changes?
I think more context might be needed to get a better suggestion, but I would assume you start your sequences in uvm_test
class in main_phase
, then one suggestion is adding your condition in a later phase like shutdown_phase
class test extends uvm_test;
// ...
task main_phase(uvm_phase phase);
phase.raise_objection(this);
// Start sequences
phase.drop_objection(this)
endtask
task shutdown_phase(uvm_phase phase);
phase.raise_objection(this);
wait(/*condition*/);
phase.drop_objection(this);
endtask
endclass
Needs little more elaboration for your use case.