How to set macro having repeated text

SystemVerilog
1

Hello Gurus,
I am looking for easier way to declare following localparams pattern by means of using SV macros:


localparam integer myvar [5:0] = '{myvar_5,
                                   myvar_4,
                                   myvar_3,
                                   myvar_2,
                                   myvar_1,
                                   myvar_0};

// There are more than 20 such declarations with different lengths, say N like so in code
//localparam integer somevar [N-1:0] = '{somevar_<N-1>,
//                                       ...,
//                                       somevar_2,
//                                       somevar_1,
//                                       somevar_0};

I would ideally like to have a SV macro `DECLARE_TB_ARRAY(var_, length_, type_) which can be used for declarations easily. But SV macros doesn’t support repeated text by means of conditional check and loops. Is there any clever alternate?

Thanks.

2

In reply to stupidkris1010:

Cannot be done in SystemVerilog using macros.

I would try figure out a way not to have individual signal names and use an array instead.

You could also look for editor scripts to generate the code for you.