How to set a flag for one clock cycle on request

SystemVerilog
4

In reply to PedroCavalcante:

if the request is high for multiple clock cycle then you will always be asserting the flag every other posedge of the clock which is not correct.

The required output is flag should be asserted high once and ony for one clock cycle when the request is asserted.

Also, though i could achieve the solution by looking at the signals like below i want something to get the signals in sync with clock.


forever begin
   @(posedge m_vif.Req);
   flag = 1;
   @(posedge m_vif.uclk);
   flag = 0;
   wait(m_vif.Req == 0);
end