How to select specific random values in class declaration?

SystemVerilog
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1 
class abc_test extends abc_base_test;
   `uvm_component_utils(abc_test)
   string report_id = "abc_test";

   rand int write_client_select;
   write_client_select = ($urandom_range(1,10));

I want to select random values from different set of values for “int write_client_select” such as 0,2,4,7,12,16,… and not range.

What is the way to do it?

2

In reply to Dharak Modi:

class abc_test extends abc_base_test;
`uvm_component_utils(abc_test)
string report_id = “abc_test”;
rand int write_client_select;
write_client_select = ($urandom_range(1,10));**
I want to select random values from different set of values for “int write_client_select” such as 0,2,4,7,12,16,… and not range. and I want to use this randomly selected value later on in build and run phase.
What is the way to do it?

3

In reply to Dharak Modi:

Try this…

randomize(write_client_select) with { write_client_select inside {0,2,4,7.12.16}; };

Pavan

4

In reply to pavan yala:

rand int write_client_select;
randomize (write_client_select) with { write_client_select inside { 1,3,4,7,8,9,10,11,12,13,14,15,17,20,21,22,23,24,25,27,29,30};};

Pavan, I tried this but getting compilation error, “**): near “(”: syntax error, unexpected ‘(’, expecting IDENTIFIER or ‘=’.****”

5

In reply to Dharak Modi:

The call to randomize must be inside a class method. Can you show your complete code.

6

In reply to dave_59:

I tried in Build phase and it worked. Thanks Dave.

7

In reply to Dharak Modi:

Pavan, Thanks a lot buddy. It’s working for me.