How to run shell script in systemverilog file

SystemVerilog
1

I have this system verilog code. This verilog code need to run shell script and this shell script will run perl script. My compilation fail because it does not produce my output file which is output.sv. Below is my verilog code

    module check_value( dut_if if );

       //Run shell script
       $system($sformatf("sh my_shell.sh"))

      //Output from the shell script   
       `include "output.sv";
   
    endmodule

Also here, I provide my shell script. just incase, it needed.

 #!/usr/bin/tcsh -f

 unset PROJECT
 perl my_perl.pl
2

In reply to Daffodil:

The $system() function is procedural and will only be executed when the design is simulated. The `include is a compilation directive and is processed when the design is compiled.

You can not mix the two. You will need to run the shell script prior to compiling the design.

3

In reply to cgales:

Thanks for the explanation! :)