Hi all,
I am new and ramping up with system verilog based verification environment. I came across a simple doubt while I was working on counter shifter verification. I have all the components working up end, each component being declared as a class. My test case is a program which is instantiated in the Top. Now the doubt I have is how do I run multiple test cases selectively. Like if I have 5 test cases, my immature knowledge tells me to instantiate all of them in the top which is mandatory in every which way. But if I don’t need all the tests to run, what do I do? Like how do I achieve a control over the regressions. Is this achieved by using some separate scripting language which gives us a handle to control the environment?
All,
I shall be more than glad to have your expert inputs.
Because programs are static constructs (fixed at elaborate time) they’ve fallen out of use. UVM models test cases as classes. Which test case to run is selected by a plusarg. A plusarg is a way to pass information to the simulation via the command line. Based on the value of the plusarg, an object of a certain class is instantiated.
Say you have the tests test1, test2, test3. You decide that you want the plusarg to be called TESTNAME. By calling your simulator with an extra +TESTNAME=test1 argument, your testbench would instantiate test1. This way you can change which test gets started without having to re-compile the testbench.
You could figure out how to implement these things for your vanilla SV testbench, but I’d recommend learning UVM, since most serious verification work is done using that. You could just start with learning how to start a UVM test and adapt your existing code to use this mechanism.