** Error: (vlog-13069) E:/uvmp/sequence_item.sv(1): near “uvm_sequence_item”: syntax error, unexpected IDENTIFIER. ** Error: E:/uvmp/sequence_item.sv(1): Error in class extension specification.

class spi_driver extends uvm_driver #(spi_sequence_item); uvm_component_utils(spi_driver) spi_vif m_vif , s_vif; spi_sequence_item packet; uvm_analysis_port#(spi_sequence_item)dut_in_pkt; //Constructor function new(string name="spi_monitor" ,uvm_component parent); super.new(name , parent); …

class spi_sequencer extends uvm_sequencer#(spi_sequence_item); `uvm_component_utils(spi_sequencer) //Constructor function new(string name=" spi_sequencer " ,uvm_component parent); super.new(name , parent); endfunction : new endclass : spi_sequencer

class spi_sequence extends uvm_sequence #(spi_sequence_item); `uvm_object_utils(spi_sequence) //Constructor function new(string name=“spi_sequence”); super.new(name); endfunction : new //Task Body virtual task body(); req=spi_sequence_item::type_id::create(“req”); start_item(req); configur…

class spi_sequence_item extends uvm_sequence_item; /* Register configuration */ rand logic [31:0]master_ctrl_reg; rand logic [31:0]slave_ctrl_reg; rand logic [31:0]divider_reg; rand logic [31:0]slave_select_reg; rand logic [31:0]start_dut_reg; /*DUT output / logic [31:0]out_master_data; log…

class spi_scoreboard extends uvm_scoreboard; uvm_component_utils(spi_scoreboard) uvm_analysis_imp_decl(_exp_pkt) uvm_analysis_imp_decl(_act_pkt) uvm_analysis_imp_exp_pkt#(spi_sequence_item , spi_scoreboard)drv2sb; uvm_analysis_imp_act_pkt#(spi_sequence_item , spi_scoreboard)mon…

class spi_coverage extends uvm_component; `uvm_component_utils(spi_coverage) spi_sequence_item c_pkt; //Coverage Details covergroup spi_trans_cg; cp_dut_mosi : coverpoint c_pkt.exp_master_data { bins byte7 = {[0:255]}; bins byte15= {[256:65535]}; bins byte23= {[65536:16777215]}; bins byte3…

class spi_agent extends uvm_agent; 'uvm_component_utils(spi_agent) spi_sequencer sequencer; spi_monitor monitor; spi_driver driver; spi_vif m_vif , s_vif; //Constructor function new(string name=“spi_agent”,uvm_component parent); super.new(name , parent ); endfunction : new //Build Phase …

include "spi_defines.v" include “timescale.v” module spi( /Wishbone signals / wb_clk_i , wb_rst_i , wb_adr_i , wb_dat_i , wb_dat_o , wb_sel_i , wb_we_i , wb_stb_i , wb_cyc_i , wb_ack_o , wb_err_o , wb_int_o , /SPI signals / ss_pad_o , sclk_pad_o , mosi_pad_o , miso_pad_i , /Scan Insertion / …

include "spi_defines.v" include “timescale.v” module spi_clock_gen(clk_in , rst , go , enable , last_clk , divider , clk_out , pos_edge , neg_edge); //scan_in0 , scan_en , test_mode , scan_out0 , reset , clk ) ; input clk_in; // input clock ( system clock ) input rst; // reset input enable; //…

// ‘define SPI_DIVIDER_LEN_8 14 define SPI_DIVIDER_LEN_16 // ‘define SPI_DIVIDER_LEN_24 // ‘define SPI_DIVIDER_LEN_32 ifdef SPI_DIVIDER_LEN_8 define SPI_DIVIDER_LEN 8 // Can be set from 1 to 8 endif ifdef SPI_DIVIDER_LEN_16 define SPI_DIVIDER_LEN 16 // Can be set from 9 to 16 endif ifdef …

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How to resolve this error

UVM

UVM, uvm-ral, UVM-callback, uvm-verilog, uvm-factory

Valmor February 14, 2019, 2:50pm 25

Oh Lord…

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