How to reference internal user typedef of VHDL DUT?

UVM
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9

In reply to S.P.Rajkumar.V:

Is your intention to observe DUT register value do decide your sequence in the driver/monitor?
I am not sure why you want to pass the register map through config_db. If you want to have access then UVM RAL is the way to go.
But if RAL is not set up for you, and you quickly want to access a couple of registers, you can use the interface approach.

  1. Add those registers in the interface,
  2. do the necessary connections using ‘assign’ at the top tb. (given that you take care of VHDL datatype (register type) conversion to logic/reg [31:0])
  3. pass on the interface to the UVM_Component through uvm_config_db::set, so the component can retrieve it and can reads the register value.

Back to this recommendation, my original problem surfaces again with the interface approach. My issue is getting the typedef visibility from the VHDL package into the interface. Because the regmap is declared with a particular typedef the interface variable would need this typedef to declare and assign a local copy.

How would I give the interface visibility to the VHDL typedef?