How to reference internal user typedef of VHDL DUT?

UVM
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8

In reply to chr_sue:

In reply to ce_2015:
I do not believe this Working. It should give you a compile errror:
vlog -mfcu +incdir+“…/hdl/proj_pkg.vhd” -f tb.f -incr -mixedsvvh
Use instead

vcom -mfcu +incdir+"../hdl/proj_pkg.vhd" -f tb.f -incr -mixedsvvh

Thank you for the recommendation. However, what you provided isn’t working either… Out of curiosity, why do you recommend using vcom instead of vlog where all of the files listed in tb.f are SystemVerilog files?

The error I get now is:


Error: (vcom-1995) Package "proj_pkg" cannot be imported in SystemVerilog designs.

I should add that the code I am using to import the package inside top is:



module top;
   import   proj_pkg::*;
   user_type_regmap register_map;
   ...
endmodule

There may be a need to also include the VHD package file inside the top? This leads to other errors though so I am not certain…