How to reference internal user typedef of VHDL DUT?

UVM
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6

In reply to chr_sue:

I suppose then my issue trying to figure out (1). For (2), the VHDL is compiled as VHDL-2008 and I can confirm that my top.sv can reference VHDL internals (it’s just getting UVM components to reference them).

Anyways back to (1), I am trying to compile the VHDL package along with my SV structure that contains the typedef using this syntax:


vlog -mfcu +incdir+"../hdl/proj_pkg.vhd" -f tb.f -incr -mixedsvvh

where “tb.f” contains the testbench files and “proj_pkg.vhd” contains the VHDL typedef of the regmap.

However, I am getting errors saying that it could not find the proj_pkg that I reference in my top:


import proj_pkg::*;

I am using Questasim.