In reply to ce_2015:
There are 2 Problems:
(1) any typedef you are using in VHDL you can make available especially using Questa in SV using the corresponding switch (-mixedsvvh) during compilation.
(2) VHDL until VHDL-2008 is not transparent from outside, i.e. it is forbidden/impossible to use a hierarchical Path from SV/UVM.
This is one of the reasons why there is the RAL in UVM.