In reply to S.P.Rajkumar.V:
Is your intention to observe DUT register value do decide your sequence in the driver/monitor?
I am not sure why you want to pass the register map through config_db. If you want to have access then UVM RAL is the way to go.
But if RAL is not set up for you, and you quickly want to access a couple of registers, you can use the interface approach.
- Add those registers in the interface,
- do the necessary connections using ‘assign’ at the top tb. (given that you take care of VHDL datatype (register type) conversion to logic/reg [31:0])
- pass on the interface to the UVM_Component through uvm_config_db::set, so the component can retrieve it and can reads the register value.
My intention is only to use the “mirror” approach in a Scoreboard to periodically compare a separately allocated regmap variable in the Scoreboard to the actual regmap in the DUT. I don’t intend for the Driver or sequencer to care do anything based on these regs. I don’t have access to RAL.
For me it is completely unclear what your intention is. If you are using the register layer you do not need what you are intending, because the register value you want to observe is in te register mirror in your UVM testbench.
I’m not using the Register Layer. I am making a “shadow register copy” in my Scoreboard that is compared with the actual registers from time to time. That is all.
The disconnect for me is how do I give the Scoreboard visibility to the VHDL’s regmap (which is declared as a user typedef. The uvm_config_db seems like the recommended method since hierarchical references are discouraged/not allowed from inside packages.