How to randomize delay and assign it to clock

SystemVerilog
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3 
shortreal rand_val;
  rand_val = $urandom_range(128)/100ns;
  `uvm_info("DELTA", $sformatf("Randomized delta: %f", rand_val), UVM_NONE)
  #rand_val itf.clk_itf[CLK_UNSHAPED].clk =~ itf.clk_itf[CLK_UNSHAPED].clk;

Can I do something like this? if yes then I’m getting following error:
Following verilog source has syntax error :
136: token is ‘=’
rand_val = $urandom_range(128)/100ns;

Thanks!