In reply to abhirula:
Ok, your question makes more sense now. SystemVerilog multi-dimensional arrays are more like arrays of arrays. That means you have to deal with each dimension separately, and each elements that is an array needs to be sized.
class A;
rand bit [11:0] width [];
rand bit [11:0] height [];
rand bit [11:0] rows_cols [][];
constraint width_cst {
width.size() inside{[100:5]};
height.size() inside {[200:700]};}
constraint c {rows_cols.size() == width.size();
foreach(rows_cols[ii])
rows_cols[ii].size == height.size();
}
constraint each_element {foreach(rows_cols[ii,jj])
rows_cols[ii][jj] inside {[1:255]};}endclass