How to pass multi-bit variable in a SVA property's arguments?

SystemVerilog
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2

In reply to rshrig:

For sequences, properties, and checkers, there is no need to specify an argument’s type. Arguments are just symbolic references similar to the way macro arguments work.

If you want to specify a particular argument type, you can do so the same as you would in a function or task.

property SAMPLE_2(Req, logic [31:0] sData, Ref_Value);

This is all explained in the LRM section 16.8 Declaring Sequences.