I’ll be using a UVM class in my question, but this really applies to SystemVerilog classes in general, so I’m posting it under the SystemVerilog category.
I’m writing a generic UVM driver that needs to work with different virtual interfaces, but only one at a time per instance. The driver’s behavior stays the same regardless of the interface - it follows a specific signal flow and pushes signals in a particular order to the correct destination in the DUT.
The block I’m driving has multiple instances across the DUT. While the basic inputs names are identical, the inputs itself are unique, and also each instance operates in a different domain. Because of that, each virtual interface needs to be specific to the instance it connects to, ensuring the signals reach the right place under the right conditions.
I initially tried using a parameterized type (type IF), like this:
class interrupts_driver #(type IF = uvm_void) extends uvm_driver #(interrupts_seq_item);
virtual IF vif;
endclass
But SystemVerilog doesn’t allow virtual on a type parameter, causing a compilation error.
I thought about just assigning the interface to a class variable from outside, but I’m wondering if that’s the right practice. Is there a better way to pass different interfaces to the same driver instance?
Would love to hear your thoughts!