How to pass a module parameter to my classes

SystemVerilog
1

Hello all,

I am building a UVM verification environment for a VHDL entity that has 1 generic. This VHDL design is encapsulated into a SV wrapper module which is parametrized. This parameter/generic is called C_COUNTER_NBIT and is used to define the size of several I/O and internal signals.

The idea is to be able to launch a simulation that is able to randomized this parameter during elaboration. I use vivado for my simulation and I’m able to specify a value in the command for the parameter of my top module. Then I pass it to the wrapper and then to my VHDL module.

The issue I have is: I can’t manage to set the parameter of my virtual interface. I tried to set the value of my interface parameter when declaring the virtual interface to the config db and/or in the instanciation of actual interface inside my wrapper but I always get the following error: incompatible complex type assignment

Here is the code I use

Thanks in advance for your answers.

module top#(C_COUNTER_NBIT = 16);
    `include "uvm_macros.svh";
    import  uvm_pkg::*;

    import tb_pkg::*;

    frame_generator_wrapper #(.C_COUNTER_NBIT(C_COUNTER_NBIT)) u_frame_generator_wrapper();

    initial begin
        uvm_config_db #(virtual Interface#(.C_COUNTER_NBIT(C_COUNTER_NBIT)))::set(null, "*", "Interface", u_frame_generator_wrapper.fr_gen_itf);

        uvm_top.finish_on_completion = 1;
        run_test("Tc_frame_generator");

    end
endmodule: top 

interface Interface #(C_COUNTER_NBIT = 8)(input bit clk);
    //Signals
    logic                           rst;
    logic[C_COUNTER_NBIT-1:0]       cfg_hor_sync_pulse;

    clocking driver_cb @(posedge clk);
        output      #1 rst, cfg_hor_sync_pulse;
    endclocking: driver_cb
endinterface: Interface

module frame_generator_wrapper#(C_COUNTER_NBIT = 16);
    bit clk;

    Interface fr_gen_itf(.clk);
    //I also tried this but it not working neither
    //Interface #(.C_COUNTER_NBIT = C_COUNTER_NBIT)fr_gen_itf(.clk);


    frame_generator #(
        .G_COUNTER_NBIT(C_COUNTER_NBIT)
    ) u_frame_generator(
        .clk(clk),
        .rst(fr_gen_itf.rst),
        .cfg_hor_sync_pulse(fr_gen_itf.cfg_hor_sync_pulse)
    );

    initial begin: clock_generator
        clk = 0;
        forever begin
            #(C_CLK_PERIOD/2);
            clk = ~clk;
        end
    end: clock_generator
endmodule: frame_generator_wrapper
2

In reply to j_lem:

In the module frame_generator_wrapper(), you need to parameterize the instantiation of Interface to match the other instantiations.


Interface #(.C_COUNTER_NBIT(C_COUNTER_NBIT)) fr_gen_itf(.clk(clk));