How to override VHDL generics using vopt -G option

SystemVerilog
, , , ,
4

I have experimented and found that I can override MY_STD_LOGIC_GENERIC with any value (eg: ‘0’, ‘1’, ‘W’, ‘X’) from the command line just by saying, for example,

-G MY_STD_LOGIC_GENERIC=W
and that I can override a std_logic_vector as such: (note the reuquired double-quotes!)
-G MY_STD_LOGIC_VECTOR_GENERIC=“24’hdefa17”
but what about other types?

[br]As I mentioned, my entity also has boolean generics and I read on another forum that boolean was like the std_logic type in that it is an enum and you simply refer to the positional value - can anyone confirm this? My experiments with setting the boolean generics have all failed.

Thanks!