How to override VHDL generics using vopt -G option

SystemVerilog
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2

Note that neither “3’d2” nor “2” are actually valid values for a STD_LOGIC data type.

In your SV parameter(generic) over ride, the 3’d2 is getting trimmed and just the LSB is getting passed.

For your command line over ride, it does not do this sort of trimming or any type conversion, the value passed must be a legal value for the generic type being used.
I would expect something like

-GMY_STD_LOGIC_GENERIC=1

to work.

If you are still having trouble, I would recommend contacting your local Mentor Support representative they will be able to help you more with specific tool usage issues.