How to monitor verilog module internal signal through uvm testbench

UVM
6

In reply to chr_sue:

//RTL Probe Interface  to be bind inside the dut
interface rtl_probe_if #(int WIDTH)(inout wire [WIDTH-1:0] shift_data);
  import uvm_pkg::*;
  `include "uvm_macros.svh"

  typedef logic [WIDTH-1:0] T;

  import rtl_probe_pkg::*;
  localparam string PATH = $psprintf("%m");
  
  //Implementation of Abstract Class
  class rtl_probe extends rtl_probe_abstract #(T);
  
    function new (string name = "");
      super.new(name);
    endfunction

    typedef uvm_object_registry #(rtl_probe,{"probe_",PATH}) type_id;
    static function type_id get_type();
      return type_id::get();
    endfunction

    function T get_rtl_probe();
      return shift_data;
    endfunction

  endclass

endinterface
//Binding in the top level module is as follows
bind fetch_engine : dut.inst_fetch_engine rtl_probe_if #(32) b1(shift_data);

yeah sure.
I’m following the same piece of code in the reference paper to tap the RTL signal.