How to monitor verilog module internal signal through uvm testbench

UVM
4

In reply to dave_59:

See my DVCon paper The Missing Link: The Testbench to DUT Connection

Hi,

Really that was helpful for my current scenario,where I need to tap the RTL signal.But, while implementing the code with reference to the paper,I ended up with the following error with the VCS tool:
Error-[BPRHS] Bad RHS expression of parameter
-I-:/rtl_probe_if.sv, 9
-I-:“PATH”
-I-: The RHS expression of the parameter could not be evaluated.
-I-: localparam string PATH = $psprintf(“%m”);
-I-: Please check for undeclared variables, nets, parameters with unknown values,
-I-: hierachical references or illegal operators.

How I can get rid of this issue.Also,why you are using the create_object_by_name instead of the available UVM macros.

Thanks in advance :)