How to merge a 2 dynamic arrays into one dynamic array without using any loops

SystemVerilog
1

my pgrm is given below
module test;
int a,b,c;
initial
begin
a = new[5];
b= new[5];
c = new[a.size+b.size];
foreach(a[i])
a[i] = i+5;
foreach(b[i])
b[i] = i+10;

 c = a;
how to assign address of c[5] to address of b
c+5 = b; // giving error
c= {a,b}; // giving error

end
in above pgrm base address of a is assigned to base address of c. but now i want address of c[5] should be assigned to base address of b. can i do this?

2

SystemVerilog does not have pointers. An array is not pointer like it is in C, it is an aggregate. When you write c = a;, you are creating a copy ofa and assigning that array as a whole to c. There is no need to new c.

**c = {a,b};**should have worked. If you are getting an error for this, please let us know what it is. It’s possible that your simulator version is not supporting the recently introduced array concatenation syntax in 1800-2009.