In reply to tw011:
It’s best to put your classes in a package and `include them instead of putting them on the command line
my_pkg.sv
package my_pkg;
`include "reg_item.sv"
`include "driver.sv"
`include "monitor.sv"
`include "scoreboard.sv"
`include "environment.SystemVerilog"
endpackage
And then replace these files with my_pkg.sv in your filelist. Also see SystemVerilog Coding Guidelines: Package import versus `include - Verification Horizons