How to Make an array of extended class (a list of test)

SystemVerilog
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3

In reply to dave_59:

Hi Dave,

Thank you for your reply.

This looks like a solution. Sadly, it kills my simulator, which then becomes a tool issue, not a SystemVerilog issue, so not a valid subject for this forum. So I’ll work on the tool and report back as soon as possible.

Thanks again,

jf