DearAll I’m trying to understanding UVM REG Model ACCESSING. https://www.edaplayground.com/x/hbg4 Firstly, to understanding .update() functionality, I add the .mirror() method as the below. then I add regmodel.update(status, UVM_BACKDOOR, .parent(this)); to update for fixing MISMATCHED between D…

In reply to UVM_LOVE : Please find a working example here (for FRONTDOOR): [image] EDA Playground Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser.

How to know backdoor access can't use or not?

UVM

chr_sue January 18, 2022, 2:08pm 8

In reply to UVM_LOVE:

Please find a working example here (for FRONTDOOR):