How to introduce a wire delay inside RTL without making any modifications

SystemVerilog
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1

Hi All,
I am trying to run a gate level simulation and it needed some delays for some of the AXI related signals inside the RTL.
Typically we will modify the RTL locally and add the required delays to get the simulations going.
I am wondering if there is any way to add the wire delays at the input of a module by using hierarchical paths of the nets
involved from the test bench? I want to know if there is any way to use the “specify” block for this. Or any other idea is also ok
for me. Thanks for your help.

2

In reply to ramkiv:

You can create a Standard Delay Format (SDF) file and use #sdf_annotate to either add or replace delays in your gate-level design. See section 32. Backannotation using the standard delay format in the IEEE 1800-2012 LRM.

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In reply to dave_59:

Thanks Dave for the suggestion. I have created a simple sdf file using INTERCONNECT , annotated in VCS. No errors or Warnings reported but the waveform doesn’t show the delay intended. Any suggestions?

ex from the sdf file:
(INTERCONNECT PM_be_bridge_top/hreadymuxm PM_fc_reg0/flfphreadys (4:4:4) (4:4:4))