How to integrate the interface of AHB VIP into SoC level?

UVM
,
9

In reply to cgales:

Thanks cgales .

it is highly recommended that you use an RTL interface for the design, and a separate verification interface for the UVM agents.

(1) Do you mean we should define 2 interfaces ::


     interface  apb_intf  (  input  clk , reset ) ; // RTL interface
         wire  [ 2:0 ] siga ;
         wire  [ 1:0 ] sigb ;
         ....................
     endinterface

     interface  verif_apb_intf  (  input  clk , reset ) ; //  Separate  verif interface
          wire  [ 2:0 ] siga ;
          wire  [ 1:0 ] sigb ;
         ....................
           //  Additional  task and  function  definitions 
     endinterface
     

 Since  these  are  **2 separate non-compatible type interface**,

how would we connect the RTL interface ( apb_intf ) signals with the separate verification interface ( verif_apb_intf ) signals ?

 i.e  In  Block-level's  Top_tb  we  would  instantiate  RTL  interface ' apb_intf ' and  connect  it  to  port  of  DUT's  instance 

     However  we  would  need  to  set  the  **separate  verification  interface**  via  config_db . 


Eg :  config_db #( virtual verif_apb_intf ) :: set ( null , "uvm_test_top"  , "apb_intf_name" , ?? ); 

     What  would  the  4th  argument  be  to  call  to  set  ?

Would there a better solution possible using bind construct ?

(2) Using bind construct what if I were to try ::


   //  Assume  Block-level  DUT  is  defined  as  ::  

       module Block_DUT ( apb_intf  intf ) ;
           ...............
       endmodule
         
 interface  verif_apb_intf  (  input  clk  ,  reset );  //  Separate  Verification  Interface 

       wire  [ 2:0 ] siga ;
       wire  [ 1:0 ] sigb ;

      //  Using  "hierarchical upward name reference"  as  discussed  with  Dave  ::
     //   verificationacademy.com/forums/systemverilog/assigning-module-variables-interface                                 
 
       assign  siga  =  Block_DUT.intf.siga ; 
       assign  sigb  =  Block_DUT.intf.sigb ; 
       .....................................

  endinterface


   Then  within  System-level  top_tb  we  simply  write  :: 



      axi_top     system_intf  ( clk , reset ) ; // Driven  via  Driver  at  System-level
 
      system_top  chip_top( axi_top );
      
      //  intf.clk  and  intf.reset  are  Interface  Signals  of  Block_DUT  ::

      bind  Block_DUT  verif_apb_intf  bind_inst ( intf.clk  , intf.reset ) ;

      initial  begin
     
       //  One  inconvenience  is  to  pass  full  hierarchy  of  Interface  ::

uvm_config_db#( virtual verif_apb_intf ) :: set( null , "uvm_test_top" , "block_vif_intf" , chip_top.subsystem_a.block_a.bind_inst );
 
       end

Would it be a valid alternative ( instead of instantiating apb_intf in System-level Tb ) ?