In reply to Have_A_Doubt:
It appears that you are using interfaces as port connections in your RTL. If this is the case, it is highly recommended that you use an RTL interface for the design, and a separate verification interface for the UVM agents. The reason for this is that the RTL interface acts as a simple wire bundle, while the verification interface will include all of your BFM tasks/functions which aren’t synthesizable.
In the reuse case, where you want to reuse the apb agent, your system-level top_tb would look like:
apb_intf intf(chip_top.subsystem_a.block_a.clk,
chip_top.subsystem_a.block_a.reset);
// Assign DUT signals to apb_intf. Note this is monitor only
assign intf.SIGNAL_A = chip_top.subsystem_a.block_a.SIGNAL_A;
assign intf.SIGNAL_B = chip_top.subsystem_a.block_a.SIGNAL_B;
axi_intf system_intf( clk , reset );
system_top chip_top( system_intf );
initial begin
// Fetched in Test where Agent config object is created and assigned to Env's config object
uvm_config_db#( virtual apb_intf ) :: set( null , "uvm_test_top" , "apb_intf_name" , intf );
uvm_config_db#( virtual axi_intf ) :: set( null , "uvm_test_top" , "axi_intf_name" , system_intf );
run_test("sanity_test");
end
You should only get() the virtual interface handles in the test as it will know the mapping of VIFs to agents. Agents should only get() their associated configuration object which contains the required VIF handle and never get a VIF handle from the config_db directly.