How to inject error in AHB master driver

UVM
,
1

How can I intentionally introduce a sequence of error injections, starting with transitions like idle and then busy, into the htrans signal within the master driver of an AHB VIP? It’s important to note that the changes in the htrans signal are determined by the transfer type, such as idle, busy, nonseq, and seq. Although I haven’t explicitly declared the htrans variable in the transaction class, I’m interested in understanding the proper procedure for simulating these specific error injections within the context of signal transitions.

2

In reply to harsh7112001:

Typically a field is added to the sequence_item which specifies if there is to be an error introduced by the driver while executing the transaction on the bus.

3

In reply to cgales:
What you mean by a field is added to the sequence_item ? Could you provide an illustration? If a new field is introduced to the sequence_item, what additional logic might need to be implemented in the driver based on the value of that variable? like if else statement we have to add.

4

In reply to harsh7112001:

It sounds like you driving these signals directly from the driver class, as opposed to driving from a bus functional model in the interface.

Here is a very simple bus. Assert req, wait for grant, drive addr and op (R/W), and wait for ack. First is the good transaction and driver.


class SeqItem extends uvm_sequence_item;
  bit [15:0] addr, data;
endclass

class Driver extends uvm_driver;
  virtual task send(SeqItem t);
    // Request bus
    vif.req <= 1;  // req asserted all the way thru transaction
    do @(posedge clk)
    while (!vif.grant)

    // Drive read or write
    vif.addr <= t.addr;
    vif.read <= t.read; // 1=read, 0=write
    if (!t.read)
      vif.data <= t.data;
    do @(posedge clk)
    while (!vif.ack)

    // Process response
    if (t.read)
      t.data = vif.data;
    vif.req <= 0;
  endtask
endclass : Driver

One possible error is dropping request early. Extend the transaction class and add a property to generate an error. Extend the driver class to process the error.


class SeqItemErr extends SeqItem;
  bit drop_req_early;
endclass

class DriverDropReq extends Driver;
  task send(SeqItem t);
    SeqItemErr e;
    if (!$cast(e, t)) `uvm_fatal("BAD", "$cast")

    // Request bus
    vif.req <= 1;  // req asserted all the way thru transaction
    do @(posedge clk)
    while (!vif.grant)

    // Error injection code
    if (drop_req_early)
      vif.req <= 0;  // Error, request dropped too early

    // Drive read or write
    ...
  endtask
endclass

There are probably a few bugs in this. but you get the overall idea.