How to handle complex bus sequences using the Register Layer

In reply to frefra:

In reply to warnerrs:
Thanks for your response!

np.

I think we agree on the fact that using some high-level sequence item is not preferable.

That’s precisely opposite of what my last sentence says.

I looked into the translation sequences and this looks like it is exactly what we need. We’re quite new to UVM, so it turned out we did not actually know the correct term for a translation sequence. So instead of an adapter we now use a translation sequence to translate a uvm_reg_item into starting some layered sequences that ultimately drive the bus.
Do you know if it is possible to also implement explicit prediction when no adapter is used?

You can embed prediction calls into the translation sequence, which would be equivalent to enabling auto_predict with a register adapter. If you want full prediction, for non-uvm_reg based transactions, you’ll need a monitor to decode the AXI activity. Yet another reason to build a high level axi_item.