How to give _weightage for variable in_verilog

SystemVerilog
1

hi,
i have one variable i.e bit error; how can i get more number of ones compare to zeros while randomization.? (i am not decalre rand keyword)

please provide logic

2

In reply to Rohi_417:
You can use any inline constraint by calling std::randomize

bit error;

std::randomize(error) with {error dist {0 := 49, 1 := 51}; };

See LRM section 18.12 Randomization of scope variables—std::randomize()

3

In reply to dave_59:

Thank you dave